1. Field of the Invention
The present invention relates in general to integrated circuit test equipment and in particular to an integrated circuit tester employing parallel processing of algorithmic instructions for controlling test signal generation and data acquisition during an integrated circuit test.
2. Description of Related Art
To test an integrated circuit or similar device under test (DUT), a typical integrated circuit tester transmits test signal pulses to various terminals of the DUT and acquires output data generated at those terminals by the DUT in response to the test signals. The acquired data may then be analyzed to determine whether the DUT is responding as expected to the test signals. Generally the transmission of test signals and the acquisition of DUT output data must be precisely coordinated.
Integrated circuit testers typically include a set of modules or "nodes", one node being associated with each terminal of the DUT. A test is organized into a set of successive time segment ("test cycles"). During any given test cycle, each node can either transmit a test signal to the associated terminal, acquire DUT output data at the associated terminal, or do neither. Each node includes its own memory for storing a sequence of commands. Each command indicates an action to be taken by the node during a test cycle--e.g. whether it is to start or stop transmitting, start or stop acquiring. Each command also indicates a time during the cycle the action is to be taken. Each node also includes circuits for sequentially reading the commands out of memory during successive test cycles and performing the indicated actions.
The nodes are typically interconnected to a host computer via a bus network. Before a test begins, the host computer executes an algorithm for generating the commands to be stored in the node memories. The host computer then transmits the generated commands to the nodes for storage in their memories. Thereafter a clock signal transmitted to all of the nodes synchronizes the nodes so that they all read the commands out of memory and perform the indicated actions in unison.
Generally a tester stores one command in each node memory for each test cycle. In recent years the size and complexity of integrated circuits have increased dramatically and so too has the length of the command sequences needed to fully test these circuits. It is not unusual for tests to run many millions of cycles and therefore require command sequences having many millions of elements. Storage requirements for such large command sequences exceed the size of memory that can be practically or economically installed at each node. Thus long tests are performed in segments with tester operation suspended between each segment while the commands for the next segment are loaded into the node memories. This greatly extends the total time and costs required for a test.
As DUT operating speeds have increased so to has the need for precise and flexible control over the timing of test signal transmission and DUT output signal sampling during each test cycle. A prior art tester includes a time formatting circuit capable of producing an output reference signal at a selected time during a test cycle. The time is selected in accordance with an input "time word"--data conveying a number indicating a particular time during a test cycle. In order to resolve time into small increments (e.g. 1/1,000,000 of a test cycle), the time word must be very long (e.g. 20 bits). For long tests, it would take too much memory to include a long time word in each command for each test cycle. Thus before the start of a test a few (e.g. four) pre-selected time words are stored in registers within each node. The four time words indicate four different times within a test cycle that an event may occur. The commands in each node thus need include only 2 bits to indicate event timing. However in such a tester system, while event timing can be accurately controlled, timing selection is limited. Such a tester cannot, for example, perform a test wherein signal timing is incrementally shifted by small amounts to determine the tolerance of a circuit for variation in signal timing without periodically stopping the test and loading new time words into the node registers.
What is needed is an integrated circuit tester which can perform a long, high speed integrated circuit test with great flexibility in timing selection but without need for large node memories.